A 47 TOPS/W 10T SRAM-Based Multi-Bit Signed CIM With Self-Adaptive Bias Voltage Generator for Edge Computing Applications

This brief presents a 10T static random-access memory (SRAM) – computing in memory (CIM) structure of 32kb macro unit for convolutional neural networks (CNNs). The proposed CIM handles ± computation with signed input signals in a single bitcell and obtains 3 times
$\Delta $
BL range for a larger sensing margin. Although the area overhead of the SRAM bitcell is 27% larger due to the positive branch PMOS, the array size is reduced to half for the same computation. A serial multi-bit weight technique is used to extend the number of weight bits with improved linearity and no significant time penalty. A bias voltage generator is implemented to regulate the discharge current under different PT variations. Both weight and input can be adjusted to 1, 2, and 4-b. For 4-b weight and 4-b input, the proposed structure achieves 85.7% accuracy with the CIFAR-10 dataset and 47 TOPS/W energy consumption in CMOS 28nm technology.