Design and Simulation of HiGBt, a 5 Gb/s SerDes for Heavy-Ion Physics Experiments

The Heavy Ion Research Facility on Lanzhou (HIRFL) and the High-Intensity Heavy-ion Accelerator Facility (HIAF) are the leading heavy-ion physics centers. The increased scale of physics experiments at HIRFL and HIAF has put forward urgent requirements on high-speed serial data transmission links. Also, the intense radiation environment is a significant challenge to commercial application specific integrated circuit (ASIC). This article presents the HiGBt, a general-purpose 5 Gb/s Serializer/Deserializer (SerDes) ASIC designed in a
$0.13 \mu \text{m}$
CMOS process for data transmission at HIRFL and HIAF. The HiGBt mainly consists of a Serializer, a Deserializer, and a high-speed clock system. The Serializer includes three stages to realize high-speed serialization. The Deserializer adopts a high linearity phase-interpolator-based structure to avoid coupling multi-voltage-controlled oscillators (VCOs). Finally, the high-speed clock system has a single event upsets (SEUs)-protected divider. The simulation results indicate that the power consumption of the SerDes is 146.3 mW, while the layout area is
$310\times 310\,\,\mu \text{m}$
.