Quaternary Reversible Circuit Optimization for Scalable Multiplexer and Demultiplexer

Information loss is generally related to power consumption. Therefore, reducing information loss is an interesting challenge in designing digital systems. Quaternary reversible circuits have received significant attention due to their low-power design applications and attractive advantages over binary reversible logic. Multiplexer and demultiplexer circuits are crucial parts of computing circuits in ALU, and their efficient design can significantly affect the processors’ performance. A new scalable realization of quaternary reversible
$4\times 1$
multiplexer and
$1\times 4$
demultiplexer, based on quaternary 1-qudit Shift, 3-qudit Controlled Feynman, and 2-qudit Muthukrishnan-Stroud gates, is presented in this paper. Moreover, the corresponding generalized quaternary reversible
$n\times 1$
multiplexer and
$1\times n$
demultiplexer circuits are proposed. The comparison, with respect to the current literature, shows that the proposed circuits are more efficient in terms of quantum cost, the number of garbage outputs, and the number of constant inputs.