A 28nm All-Digital, 1.92-7.32mV/LSB, 0.5-2GS/s sample rate, 0-latency Voltage Sensor with Dynamic PVT Calibration for Wide-range Adaptive Voltage Scaling

On-chip supply-voltage droops induced by work-load variations are severe in processors that the $1^{\text {st}}$ droop may cause up to 137 mV voltage reduction during 10 ns [5] (Figure. 1 top left). All-digital fully integrated voltage sensors are favored over analog comparators [1] for SoCs for their higher speed and resolution, either based on digital CMOS delay lines [2, 3, 4] or ring oscillators [5]. High-speed voltage sensors for droop detection face three challenges: (1) The sampling counter of the ring oscillator caused several cycles of latency and load imbalance thus increasing output jitter. (2) The process, temperature and linearity of voltage (PVT) variation cause oscillation times per cycle to vary, requiring large calibration costs. (3) The detected voltage sensor output always endures several cycles of latency from real droop occurrence, leading to delayed response.