A 2.6GHz ΔΣ Fractional-N Bang-Bang PLL with FIR-Embedded Injection-Locking Phase-Domain Low-Pass Filter

The all-digital fractional-N bang-bang PLL (BBPLL) enables low-complexity frequency generation and modulation but requires a high-resolution digital-to-time converter (DTC) to mitigate in-band noise degradation caused by a nonlinear bang-bang phase detector (BBPD) [1]. The high-resolution DTC, however, is highly sensitive to PVT variations and requires complex nonlinearity calibration or compensation methods [2]. Even with the complex calibration, an inverter-based DTC is vulnerable to a sudden supply jump due to onchip digital switching noise in SoC design and has difficulty in achieving good time resolution with low-voltage design. This work presents a DTC-free ΔΣ fractional-N BBPLL using an FIR-embedded injection-locking (FIR-IL) phase-domain low-pass filter (PDLPF) with following advantages. (1) It effectively attenuates the quantization noise, suppresses noise aliasing by the second divider and improves the in-band phase noise of the BBPLL. (2) It achieves good fractional spur performance even without nonlinearity calibration. (3) Not sensitive to mismatches and nonlinearity, it is suitable for low-voltage design with advanced CMOS technology.