A 243μW 97.4dB-DR 50kHz-BW Multi-Rate CT Zoom ADC with Inherent DAC Mismatch Tolerance

Wireless sensor nodes in battery-powered lnternet-of-things (1oTs) applications require high-resolution ADCs with a wide dynamic range (> 90dB), a moderate bandwidth ($\sim$50kHz), and very high energy efficiency ($\sim$180dBFoM). These requirements could be achieved by using continuous-time (CT) zoom ADCs that hybridize a SAR ADC and a CT delta-sigma modulator ($\triangle\Sigma$M) [1] –[3]. By combining the coarse and fine DACs with a data-weight averaging (DWA), it achieves high linearity and resolution. However, the complexity and power consumption of the DWA algorithm increases significantly with the multi-bit level of the DAC, and this can be exacerbated at lower OSR conditions. This paper presents a multi-rate CT zoom ADC architecture with inherent DAC mismatch tolerance. The proposed ADC uses a first-order CT-$\triangle\Sigma$M as the coarse ADC, and then its outputs are filtered by an 8-tap F1R DAC, resulting in inherently linear multi-bit output. The associated latency is suitably mitigated by increasing the sampling rate of the coarse $\triangle\Sigma$M. Measurement results show that the ADC can support a 2. 4Vpp differential full-scale input from a 1. 2V supply and achieves 92. 0dB SNDR, 92. 3dB SNR, and 97. 4dB DR over 50kHz bandwidth. lt consumes only 243$\cup$W, which corresponds to a Schreier FoM of 180. 5dB.