Control Gate Device Leakage Reduction by Improving Polysilicon Etch Uniformity and Active Area Recess

Periphery CMOS device control gate polysilicon etch is one of the key steps in NOR memory processing that has significant impact on device leakage current. In this paper, we discuss a method to reduce polysilicon etch aggressiveness and improve polysilicon etch rate cross-wafer uniformity. With a design of experiment (DOE) model by using electrostatic chuck (ESC) temperature and O
2
/inert gas flow in a plasma etch process, we predict inline responses and device electrical performance. A new combination of these two parameters shows a 3%-line yield improvement due to device leakage current reduction by preventing over-etching and etch punch-through damaging device gate structure.