Threshold Voltage Variation due to Tailing Effect in SOI Thin Film

Threshold voltage variation was observed on a NMOS transistor with effect correlated to the substrate high energy well implantation of a Silicon On Insulator technology. Investigation points to the tailing effect resulted from the penetration of the implanted ion through the sidewall of the photoresist and landed on the SOI thin film instead of on the substrate, which degraded the device performance seen in threshold voltage. This paper will present a study describing how the threshold voltage of transistor can be stabilized by layout change to prevent the unwanted dopants from diffusing into the channel region. This is an important learning especially for Silicon On Insulator technology with high energy implant into the substrate because of the implant tailing effect.