Post-Etch Yield Killer Defects in 3D NAND High Aspect Ratio Etching Process

The 3D NAND architecture stacked with 2-deck vertical channels array structures above CMOS device was fabricated. With developing the integrated structure, a specific post-etch defect type was easily observed in some kinds of high aspect ratio etching processes. The defect adder poses a substantial yield risk due to its subtle physical characteristics with array underlying films punched. Upon the reviewing of overall defect classified bins, the defect adder is related to the film bump defect, which would induce organic resist incompletely covered on the bumped topography and form de-focused spot during lithography. Where the resist de-focused spot located would be generated the damage pits in etching, especially, during high aspect ratio etching process to produce seriously broken underlying films. The identifications and the suppression treatments from the resources of such defect of interest are presented.