Reducing Merged Silicon-Germanium (SiGe) Epitaxial Growth in FinFETs to Avoid Yield Loss

When FinFET technology reaches 14nm and beyond, we see more and more front-end-of-line (FEOL) defects at the transistor level rather than in the back-end-of-line (BEOL) interconnect. Those small nanoscopic defects tend to have a significant impact on the yield and reliability of the final chiplets. In this paper, one unique defect of "Merged EPI" seen in the process of selective epitaxial growth of silicon-germanium (SiGe) on source/drain (S/D) regions was found to be closely related to the formation of holes in the source/drain regions. These holes cause back fill of gate metal materials and defect limited yield loss. We examine possible forming mechanisms and process factors contributing to merged epi defects, including SiGe growth kinetics on Si (100) and (111) surfaces and the local Si open ratio loading effect. Controlled experiments demonstrate an exponential correlation between the ratio of SiGe lateral width and B% concentration in SiGe film and merged epi defect density, highlighting a potential quality control parameter to reduce merged epi formation and related yield loss.