Gate and Contact Induced Drain Leakage at High Voltage Operation in DRAM : YE: Yield Enhancement/Learning

Improvement of retention time, speed and standby current in DRAM poses a significant challenge due to gate leakage which needs to be overcome as it effects the transistor performance. This paper elucidates one of the very intrinsic issues of misalignment coupled with scaling down of the technology and is responsible for high gate induced leakage in the CMOS transistors. Addressing the issue with improved registration and optimized gate length has been discussed. In addition, the paper aims at understanding the process element that leads to the agglomeration of the cobalt and titanium silicide which coupled with misalignment worsen the leakage. Furthermore, it discusses the impact through package level testing and performance.