0.4-1 GHz Subsampling Mixer-First RF Front-End With 50-dB HRR, +10-dBm IB-IIP3 in 65-nm CMOS

Reconfigurable subsampling mixer-first RF front-end is a potential candidate for low-power applications as it operates at a low clock frequency and hence consumes low power. However, the subsampling down-conversion has not been employed in mixer-first RF front-ends due to the disadvantage of high noise figure from inherent noise folding and lack of RF port impedance matching because of nonzero IF down-conversion. To address the above two issues, first, a subsampling multipath down-conversion mixer scheme is proposed for rejecting
$3f_{s}/4$
and
$5f_{s}/4$
down-conversions, thereby alleviating the effect of noise folding, leading to low noise figure. Second, an IF-stage impedance matching scheme is proposed that provides
$50~\Omega $
matching at the RF port of the mixer using an IF-LNA in shunt with an
$M$
-phase switch-capacitor filter. The analysis of the proposed scheme in terms of noise figure, conversion gain, and harmonic rejection is presented. The proposed subsampling mixer-first RF front-end is implemented in 1.2 V, 65-nm CMOS technology. The prototype occupies an active area of 0.33 mm
²
, the switch-capacitor mixer and
$M$
-phase filter consume
$400~\mu \text{W}$
of power, and IF amplifier and nonoverlapping clock generation circuit consume 25 mW and 6–12.6 mW of power, respectively. The RF front-end achieves a 6.5-dB noise figure, 15.1-dB conversion gain, 50-dB harmonic rejection ratio (HRR), and +10-dBm IB-IIP
₃
.