Design of Electrostatic Discharge Protection for Electronic Systems

The on-going miniaturization of very large scale integrated (VLSI) circuits enhances the susceptibility of these devices to damage caused by both the direct and indirect effects of electrostatic discharge (ESD). Protection networks, integrated at the chip level, effect some degree of protection for the integrated circuit and properly managed static control programs allow the devices to be safely assembled at the board level in the manufacturing environment. Effective protection of an electronic system which must function, in its packaged form, in an uncontrolled static environment, typical in consumer product applications, requires special attention, beginning at the design stage. It is necessary to accurately model the physics of the electrostatic discharge for a given electronic assembly in order to predict the level of protection required. An opportunity exists to realize enhanced system ESD protection with minimum cost using the concept of integrated protection, implemented at the circuit, circuit carrier, system input/output, system software and mechanical packaging levels. A discussion of these concepts, with specific examples, will be given.