A Highly Efficient E-Band CMOS Frequency Tripler With a Third Harmonic Boosting Technique

An
$E$
-band CMOS frequency tripler with a third harmonic boosting technique (THBT) is presented to simultaneously improve the conversion efficiency (CE) and output power. The THBT is theoretically analyzed for increasing a conversion gain (CG) and reducing the design complexity of the CMOS tripler. The gain and stability of the buffer amplifier in the proposed tripler are improved by using the capacitive charge neutralization technique with an insensitive variation of the capacitance. The differential configuration and transformer-based matching networks in the tripler suppress the fundamental and even-order harmonic signals without an additional filter. The proposed tripler, fabricated using 65-nm CMOS technology, showed a maximum CE of 10.89% for an input power of 6.5 dBm at 71.1 GHz. The maximum output power and CG were measured to be 9.9 dBm and 4 dB, respectively.