A Fully Linear PLL for Power Electronics Applications and PLL Tuning Guidelines Along with Comparative Study of Different Phase Detection Methods

This paper presents the Phase Locked Loop (PLL) nonlinear control design problem for power electronics applications. The paper proposes a new design method that transforms the whole solution to be a simple linear control problem of tracking a ramp. This completely solves the PLL pulling out of synchronism issue and the dependency of locking time on how close the PLL initialization speed is to the actual speed. This allows the PLL to have a faster tracking of the speed while increasing the system’s immunity to harmonics at the same time. Different design methods for PLL controller gains tuning are also discussed along with the linearization approaches in the literature. The proposed technique is then compared to different designs in the literature where the superiority of the newly proposed technique is proven and highlighted.