Low power, high speed PLL fabricated in UTSi/sup (R)/ process

A CMOS phase locked loop (PLL) design achieves GHz performance, low phase noise, low spurious side-bands and extremely low power (1V, 1GHz, and <1mA of current.) The design is fabricated in 0.5/spl mu/m UTSi/sup (R)/ SOI process which has been previously described [Reedy, 1999].