Multi Level Cell Reliability in Ge-rich GeSbTe-based Phase Change Memory Arrays

In this paper we analyze the Multi-Level Cell (MLC) capability in Phase-Change Memory 4kb arrays based on Ge-rich GeSbTe alloys featuring high temperature data retention. Two Ge-rich alloys with a different amount of Ge are investigated and their MLC performances are compared with standard
$\mathbf{Ge}_2 \mathbf{Sb}_2 \mathbf{Te}_5$
. Both Ge-rich materials feature a comparable data retention performance at 250°C in 1bit/cell mode, making them suitable for embedded automotive applications. Single pulse and Program-and-Verify MLC approaches are investigated to achieve 2 bits/cell. We compare the final distributions of the cell resistance levels and their evolution (drift) in time and in temperature. Finally, we show how the engineering of both materials stoichiometry and MLC programming strategy enable four distinguishable resistance levels even after one-hour bake at 150°C. These results prove MLC capability in Ge-rich GeSbTe PCM arrays.