Voltage Ramp Stress Test Optimization for Wafer Level Hot Carrier Monitoring in FinFET

Inline voltage ramp stress (VRS) is used for fast wafer level reliability (fWLR) monitoring. For hot carrier injection (HCI) degradation, saturation current is monitored as drain and gate voltages are gradually increased. NFET VRS HCI is consistent with constant voltage stress (CVS) model, while PFET CVS model and VRS slope exhibits a large discrepancy. Similar to CVS data at short stress times and low gate voltage (Vg), the discrepancy is due to electron trapping during VRS when gate bias is less than drain voltage (Vd). As the gate voltage increases, the charge-trapping component reduces giving a better correlation for VRS slope versus the CVS model.