Characterization of Backside ESD Impacts on Integrated Circuits

Si-substrate backside of an integrated circuit (IC) chip becomes an open surface for electrostatic discharge (ESD) impacts in flip-chip assembly. This paper proposes an experimental framework for characterizing backside ESD impacts on test IC chips. An off-chip controllable high voltage pulse injector (HVPI) impacts flip-flop register files (FFs) as the on-chip victims. The HVPI produces a voltage spike with the peak amplitude up to 670 V and emulates spontaneous or intentional ESD occurrence. The voltage pulse with the height of 414 V induces bit flips among FFs when it is impacted on the Si backside and targeted around the cluster of FFs. The HVPI is held on an automated X- Y -Z stage and finely positioned on the Si backside. According to the physical layout of FFs with a total of 720 bits, the induction of bit flips is confirmed to be selective and localized.