Current Injection Effect on ESD Behaviors of the Parasitic Bipolar Transistors inside P+/N-well diode

The utilization of parasitic bipolar structures inside a typical P+/N-well as an additional electrostatic discharge (ESD) path is explored. The optimization on the lateral PNP (LPNP) is discussed. Device transmission line pulse (TLP) characterizations and technology computer aided design (TCAD) simulations by Silvaco have been performed to investigate the stand-alone LPNP ESD performance and effects of the base current injection on ESD behaviors of parasitic bipolar transistors.