Device Design Aware and Interface Thermal Resistance Assisted Self-Heating Analysis in Nanosheet FET

The nanoscaled geometrical confinement of the Nanosheet FET (NSHFET) has severely aggravated the self-heating effect, affecting the device's characteristics, such as lattice temperature, thermal contact resistance, and drive current. In this paper, we investigated the self-heating effect (SHE) in the NSHFET using well-calibrated TCAD models. We analyzed (i) the behavior of spatial device lattice temperature (TD) gradient in a gate-all-around (GAA) NSHFET; (ii) the impact of varying the drain, source, and gate electrode thermal contact resistances
$(\mathrm{R}_{\text{th DSG}})$
. (iii) a fair comparison of electrical and thermal characteristics of SOI FinFET, bulk FinFET, and NSHFET based on the percentage change in subthreshold slope (SS), drain-induced barrier lowering (DIBL), drain current, etc. Further, we proposed the design guideline to mitigate SHE-induced thermal degradation in Nanosheet FET.