CNTFET Based M-DMTGDI (CMDMTGDI) Design and Its Leakage Analysis

This work presents CNTFET based Modified DMTGDI design and CNTFET based DMTGDI design, referred to as CMDMTGDI design and CDMTGDI design respectively. The proposed CMDMTGDI overcomes the contention issue in CDMTGDI design. Further leakage reduction techniques-LECTOR, GALEOR and LCNT are proposed for CMDMTGDI design. 2-input type A NAND, NOR and XOR gates are used for simulative investigation using HSPICE tool with 32nm CNTFET Stanford model at 0. 9V and 5fF load capacitance in static and dynamic mode. A maximum PDP reduction of 97.65% and 97.85% is achieved using CDMTGDI and CMDMTGDI as opposed to their CMOS counterparts. The proposed CMDMTGDI design achieves a maximum PDP reduction of 96.62% as compared to its C-DMTGDI counterparts. Further a maximum leakage power saving of 46.52%, 46.68% and 46.5% is achieved using LECTOR, GALEOR and LCNT respectively as compared to its CMDMTGDI counterparts in static mode. Corresponding values are (40.65%, 40.94%, 40.75%) in dynamic mode.