FPGA Implementation Of a High Throughput Low Power Advanced Encryption Standard (AES-128) Cipher

Ensuring secure transmission and storage of digital information is critical for any organization to function properly. To address this issue, encryption algorithms are commonly used. Advanced Encryption Standard (AES) has been globally adopted as the mainstay cipher algorithm for securing transmission networks and storage devices due to its easy implementation and compatibility with both hardware and software applications. Another reason for its widespread popularity is its uncompromisable nature against existing brute force attacks, making it practically unbreakable on existing computing power. AES implementation for battery operated devices requires an algorithm with low power consumption and high-speed encryption/decryption of digital data. This paper proposes an FPGA implementation of a high throughput parallel pipelined 128-bit AES algorithm with a low power key expansion mechanism for iterative stages. A 128-bit symmetric key has been used for undertaking 10 rounds of transformations. All the encryption and decryption transformations are simulated using iterative design methodology in order to minimize hardware consumption. Xilinx Artix-7 FPGA device is used for hardware evaluation and Verilog HDL for programming. Simulation and synthesis task has been performed on Xilinx Vivado v2021.1 IDE. The results exhibit high-rate encryption of 68 Gb/s and low energy consumption of 7 pJ/bit.