Design Analysis of 3-Bit Flash ADC using Low-Offset and Low-Power Opamp

This paper presents a unique 3-bit Flash Analog to Digital Converter (ADC) required in signal processing applications designed with the help of two stage operational amplifier as comparator designed on 90nm technology on Cadence Virtuoso and priority encoder designed using ratioed logic. This flash ADC can operate at low supply voltage of 1.2V. The other advantage of this ADC is in terms of ratioed priority encoder which results in the reduction of number of transistors. The comparator is simulated with 1.2V supply voltage at 27°C. The significant merit of the designed comparator is its low offset voltage of 1.9328mV, overall power dissipation of 22.49uW and bandwidth of 2.39KHz on 90nm technology. The comparator has been designed on both 90nm and 180nm technology and compared. For power dissipation of comparator designed on 90nm technology, Monte Carlo simulation is done with 200 samples and process variation is done at different corners. Flash ADC is simulated on 1.2V supply voltage using 90nm technology with power dissipation of 662iiW.