Formal Arbitration and Data Integrity Checking of a SpaceWire Router IP-Core

Verification of Register Transfer Level (RTL) designs is still a challenging task. Even today, simulation is often considered the only viable option for verifying designs before implementation. Thereby, Formal Property Verification (FPV) provides an additional verification approach. Capable of addressing simulation-specific problems like incompleteness and frequently able to be more efficient concerning complexity and consumed time. This paper shows how FPV is applied to prove the major functionality of a SpaceWire router which covers packet arbitration and data integrity properties. On one hand, the paper includes basic approaches to allow property definitions for packet-based designs. On the other hand, typical FPV problems like system complexity issues are discussed and possible solutions are outlined.