Analysis of HCD Effects for NMOS Transistor with Technology Scaling

Hot carrier degradation (HCD) is a significant cause of concern regarding the reliability issues for metal oxide semiconductor field effect transistors (MOSFETs) in the nanoscale technology. When the critical gate dimension length gets shorter, this degradation process worsens because the local electric field gets more substantial than the long-length gate dimension. This article investigates the effects of physical shrinking on the reliability of MOSFETs over many generations of technology, as well as the effects of process and parameter variations on the oxide-trapped substrate current and the threshold voltage for NMOS transistors. Furthermore, a recent prediction model for HCD concepts based on the typical Lucky electron model is discussed. This lucky electron model examines the implications of oxide-trapped substrate current scaling for 65 nm, 45 nm, and 32 nm technology nodes. There are also several solutions provided for dealing with HCD issues. The lightly doped drain (LDD), along with some fiddling with the power supply and the threshold voltage, may help to achieve optimal HCD performance.