A 0.4-to-30 GHz CMOS Low Noise Amplifier With Input-Referred Noise Reduction and Coupled-Inductive-Peaking Technique

This letter reports a broadband low-noise amplifier (LNA) with input-referred noise reduction and coupled-inductive-peaking technique in a CMOS technology. First, a combination of resistive-feedback and inductive-degeneration technique is proposed to mitigate the input-referred noise. The high-frequency noise currents generated by the feedback resistor and input transistors are partially suppressed by a gate inductor. Second, the LNA utilizes a two-stage coupled-inductive-peaking technique to achieve high and flat
$S_{21}$
. The chip is fabricated in a 55-nm CMOS technology. It achieves a peak gain of 20.3 dB with a 3-dB bandwidth of 0.4-to-30 GHz and a minimum NF of 2.5 dB. The output-referred 1-dB compression point (OP1dB) is
$\ge $
–8 dBm over the entire 3-dB gain bandwidth. The chip consumes a total power of 23.5 mW under a 1.5 V power supply. The core circuit occupies an area of 0.39 mm2.