An Efficient Clock Gated RSFQ Matrix Multiplier through FPGA Implementation

Multiplier are one of the indispensible component in Arithmetic and Logic Unit. Many applications for image and signal processing use matrix multiplication as their core operation. In order to speed up current solutions and adhere to real-time limitations. The proposed system depicts, the Field Programmable Gate Array features a clock-gated matrix multiplier. The clock-gating approach is used to impact a large number of bit-slicing multipliers in the suggested multiplier. The major goal of this clock-gating technology is to increase performance and decrease power consumption. This suggested multiplier's output bits be restricted to 16 bits. The fundamental gates like XOR,AND, D-flip flops and complete adders are used to create the multiplier that is being given. The multiplier design that is suggested is put into practise using the Altera Quartus II supporting platform.The CMOS uses two distinct technologies., such as 65nm and 90nm, are taken into consideration when developing the multiplier. Similar to this, the designing methodologies use two separate FPGA devices, Cyclone and Stratix. By testing the metrics such as delay, area and power, the proposed design is assessed.