Optimization And Power Delay Analysis of Different Full Adder Circuits

An arithmetic circuit is made up of several adders. A digital system’s overall performance is significantly influenced by the performance of an adder. High care must be used when creating these adder cells because any alteration to the adder cell would reduce the overall performance of the intended circuit. Therefore, even little power savings result in significant power savings and improved circuit performance. In order to reduce power consumption with high-speed operation, a number of strategies are put into place as the technology is progressively scaled down. The numerous complete adder circuits have been examined in this work. The power usage and transistor count of the simulation results generated with Micro wind are compared. These performance results will facilitate the circuit designer to settle on right adder for their required application need.