Truncated Booth Multiplier Design Of Approximate Compressors Using Verilog Hdl

High radix Booth encodings significantly reduce the number of incomplete products produced during multiplication. The employment of high radix Booth encodings is hampered by the production of hard multiples, which adds extra latency and power. In order to avoid the creation on hard multiples, the approximate radix-256 Booth encoding was suggested in this short. Partial product pairings are created using a partial encoding method and are simply acquired by shifting and complementing. The sum of each pair of matching partial products consequently takes the role of the precise encoding values. For performance testing, a 16/16-bit multiplier with the suggested radix-256 Booth encoding have been constructed.