Physical Insights of Si-Core-SiGe-Shell Gate-All-Around Nanosheet pFET for 3 nm Technology Node

This article presents a physics-based simulation study of a Si-core-SiGe-shell gate-all-around (GAA) nanosheet FET (NSFET). The numerical simulations employ various models including 1) an elastic model for lattice mismatch-induced stress in the core/shell structure; 2) the
${k}\cdot {p}$
method with a Poisson solver for the electrostatics; 3) Kubo-Greenwood model for low-field mobility calculation with surface roughness fit with experimental results; and 4) multi-subband Boltzmann transport equation (SBTE) for the high-field transfer characteristics. The study evaluates the effect of channel/wafer orientation, Ge component ratio
${x}$
in SiGe-shell region, core thickness
${T} _{\text {core}}$
, and surface roughness on electrostatics and transport properties. The Si/SiGe core/shell structure can be an additional performance knob for advanced technology node beyond 3 nm due to the following key physics: 1) thin SiGe-shell region with a high Ge component ratio tends to exhibit higher compressive stress in the shell region due to lattice mismatch; 2) holes are mainly confined in the SiGe-shell region under compressive strain at ON-state, leading to a significant enhancement in
${I} _{ \mathrm{ON}}$
for pMOS devices; and 3) core/shell devices exhibit lower hole density at OFF-state in the channel compared with Si-channel device, resulting in current leakage reduction. Finally, the proposed Si-core-SiGe-shell pMOS device achieves a 30.5% enhancement of
${I} _{ \mathrm{ON}}$
at
${T} _{\text {core}}= {3}$
nm and
${x}$
= 0.1, and two orders of magnitude higher ON- OFF ratio at
${T} _{\text {core}}$
= 2 nm and
${x}$
= 0.1, compared to the single Si-channel pMOS device. The results suggest that the proposed core-shell structure is a potential candidate for 3-nm node pMOS and beyond.