A Hybrid FA for High Performance Arithmetic Application

This research introduces a novel hybrid CMOS design model for a 1-bit full adder that addresses the requirements for improved noise-robustness, enhanced drivability, and reduced power consumption in deep submicron technology. The adoption of a hybrid style based on CMOS was explored to fulfil the desired performance of implementing new, fully-featured adders. More freedom to concentrate on different applications allows designers to drastically cut design efforts. There exist various unique designs for the full adder (FA), but this research proposes a new FA design implemented using CMOS technology with 90nm. The design employs an XOR-XNOR circuit that produces exclusive OR/exclusive NOR full-swing outputs and is utilized to construct FA is presented first. The proposed work offers improvement in latency and power delay products by 6.27 to 38.24 and 13.27 percent, respectively, over the prior design.