Ring Oscillators based All Digital Phase Locked Loop: A Comparative Study

A phase-locked loop system (PLL) is a circuit in which the output signal’s amplitude and frequency are supposed to lock with the input reference signal. Analog or digital methods can be used to construct a phase-locked loop. Due to the constant scaling down of CMOS technology, it is now advantageous to implement digital phase-locked loop devices (DPLL) because digital designs suit modern technology needs such as low power consumption, small size, and the manufacturing of integrated circuits on small chips. Unlike an analog system, which is difficult to modify, digital design characteristics can be simply changed to meet the needs of the system. This study investigates all-digital phase-locked loop systems (ADPLL), which are more scalable, portable, have a faster lock time, and are employed in most applications. The different ways of implementing a digital control oscillator and phase detector are investigated to explore the multistage designs for specific applications.