Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS

Power dissipation in the modern integrated circuits (IC) is an important parameter to determine the performance inside a chip manufactured using $\leq$65nm process technology, where the on-chip static power happens to be significantly high. In case of a processor the majority of on-chip components are sequential parts like memory, registers, counters and flip flops where the basic building block is a Data-latch (viz., D-latch). This latch is made of a good number of transistors which is why its static power consumption is comparably higher at lower CMOS nodes. Due to the emphasis on the low gate count design, 2 prominent architectures of 4T and 5TD-latch are revisited in this article to record lower static (or leakage) current, which is intended to curb down further. Accordingly an improvised circuit configuration incorporating LECTOR is unveiled due to its capability of alleviating static power of 4T and 5TD-latch by 45.04% and 18.29% respectively.