Design, Analysis and Optimization of CMOS Full Adder Based FinFET 10 nm

The miniaturization of transistors at the Nanometric scale has caused adverse effects on the performance of devices. Researchers have proposed new structures such as FinFET with multi gates on Semiconductor on insulator (SOI) and using dioxides with high dielectric constants to overcome this problem. One of the most important elements in digital electronic circuits is the full adder which has undergone important improvements to its structure in terms of speed, power consumption and chip area. In this paper, we analyze firstly the performance of FinFET 10 nm based on the ratio (I
ON
/I
OFF
). The analysis is done on Microwind 3.8 software using Predictive Technology Model ((PTM) parameters. An optimization study in terms of time delay shows the decrease of this parameters with the decrease of supply voltage on CMOS NOT gate and on a full adder with 10 transistors. The proposed design of full adder can work well at a supply voltage of 0.7 V with a time delay of 70 ps.