Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages

STT-MRAMs have emerged as the leading candidate of on-chip technology for nonvolatile cache applications. In this paper, DMTJs are used to build STT-MRAMs at the circuit level with a reduced switching current benchmarking the TFET technology model and a calibrated 10nm-FinFET technology model to explore the best configuration in the ultralow voltage domain for writing operation in terms of energy-efficiency and area. Simulation results showed that the TFET-based solutions are the most energy-efficiency in terms of the EDP index with an average EDP 57.77% lower than the FinFET-based configurations. TFET-based bitcells had a 40.23% smaller delay and 34.11% less writing energy compared to the FinFET counterparts. Finally, a standby power analysis was carried out.