Design of new DSP instructions and their hardware architecture for the Viterbi decoding algorithm

This paper proposes new DSP instructions and their architecture which efficiently and rapidly implements the Viterbi decoding algorithm. The proposed architecture, supporting typical signal processing functions as in existing DSP chips, consists of an array of operational units and data path structures adequate to the Viterbi algorithm. While existing DSP chips perform Viterbi decoding at the rate of about several dozen kbps, the proposed architecture can give the rate of 6.25 Mbps on 100 MHz DSP chips, which is nearly the same performance as that of custom-designed Viterbi processors. Therefore, the architecture can meet the standard of IMT-2000 having the 2 Mbps data rate. The proposed architecture will be implemented in the form of an ASDSP (Application-Specific Digital Signal Processor) chip.