Warpage Estimation and Demonstration of Panel-Level Fan-Out Packaging With Cu Pillars Applied on a Highly Integrated Architecture

Fan-out panel-level packaging (FO-PLP) has become a critical forward-looking technology because it can meet the demands for small size, high input–output counts, and multichip functions. Moreover, a 3-D stacked architecture called packaging-on-packaging can be achieved using the interconnects of Cu pillars. The serious warpage issue of FO-PLP during the manufacturing process, however, causes many problems, such as assembly difficulty, low device reliability, and poor product yield. To address these problems, this study presents a process-oriented finite element analysis (FEA) method to estimate the variation of the whole warpage resulting from the mismatch among the coefficients of thermal expansion (CTEs) of dissimilar materials during the fabrication procedures. Notably, the model construction of the complex redistribution layer (RDL) in the proposed FO-PLP encounters a serious challenge when the simulated estimation is performed. Consequently, an equivalent mechanical characteristic extracted through simulation is adopted to redefine the material properties of RDL and Cu pillars separately. Moreover, the modified Timoshenko bi-layered theory is employed with the process-oriented FEA of FO-PLP to clarify the stress-free temperature of the equivalent RDL. An actual FO-PLP vehicle with Cu pillars is fabricated and measured to demonstrate the reliability of the proposed simulation methodology. An average deviation of less than 10% is obtained between the simulated prediction and experiments. The results of factorial design indicate that the mechanical properties of dielectrics and RDL are the dominant factors and have an interactive effect on the warpage magnitude of FO-PLP.