Effect of Dummy Gate Bias on Breakdown Voltage and Gate Charge of a Novel In0.53Ga0.47As/InP Trench-Gate Pentode Power Device

In this article, the effect of dummy gate bias of a novel In0.53Ga0.47As/InP heterostructure trench-gate pentode power device is investigated by TCAD simulations. The dummy gate relaxes the electric field at the main trench-gate corner and increases the Off-State breakdown voltage (
$\text{V}_{\mathrm {BR}}$
) of the optimized device for improved reliability. It is shown that the device offers a 27.4% and 16% increase in
$\text{V}_{\mathrm {BR}}$
compared with the conventional silicon-based trench-gate device and the In0.53Ga0.47As/InP heterostructure trench-gate device without the dummy gate respectively. We demonstrate that the use of a dummy gate within the high-field, wide bandgap region reduces the Off-State leakage current in InGaAs/InP MOSFET. The proposed pentode device has a lower feedback capacitance and a 91.9% decrease in the gate to drain charge (
$\text{Q}_{\mathrm {GD}}$
), thus reducing the switching loss. It is thereby improving the static figure of merit (FOM)
$V_{\mathrm {BR}}^{2}/\text{R}_{\mathrm {ON}}$
(here
$\text{R}_{\mathrm {ON}}$
is the ON-resistance) by
$19\times $
and reducing the dynamic FOM
$R_{\mathrm {ON}} \times \text{Q}_{\mathrm {GD}}$
by
$151\times $
, respectively, for power switching application.