Compact Model of a Bulk FinFET Quantum Dot Toward Single Chip Integration of Qubits and Control Electronics for Quantum Computing Applications

In this work, we thoroughly investigate the drain current oscillations induced by quantum confinement in short channel bulk FinFETs, while operating in coulomb blockade (CB) regime at cryogenic temperature. Various device geometries and layouts of narrow fin-based FinFETs are analyzed experimentally to comprehend the development of quantum dots (QDs). The results demonstrate that the size of QD in the channel is crucial in defining the sensitivity of confinement-related parameters to modifications in device design. To capture the gate and drain bias dependence associated with drain current oscillations in CB regime, we have proposed analytical equations to augment the existing BSIM-CMG compact model. Model-hardware correlation is also presented for n- and p-type bulk FinFETs with different device geometries. The proposed model marks the initial steps toward developing a unified compact model that accurately captures both: the classical behavior of bulk FinFETs and its QD-based tunneling behavior at cryogenic temperatures.