An Energy Efficient High-Performance CMOS Transmission Gate Full Adder Circuit

With continuous enhancements in single integrated circuit chip applications like high speed computing techniques, data communications, large storage, micro-electromechanical systems, ultra-high frequency, high speed networking, fuel efficient automobiles, cryptocurrencies, digital signal processing, consumer electronics, secured cryptography, robotics, space applications, smart health monitoring systems, smart buildings, and internet of things, there is a need to push the transistor to conduct to the boundary limits of operation to achieve more efficient, more powerful and more intelligent integrated circuits. Real time processing of multimedia signals employs power hungry algorithms such as fast-fourier algorithms, inverse discrete cosine transforms and discrete cosine transforms. They are used to realize multiplier and subtraction logic functions on the chip. Hence adder logic is very crucial in the efficient implementation of these algorithms. In this work the design and simulation of conventional CMOS full-adder and proposed transmission gate buffered full-adder logic circuit is carried out in cadence virtuoso tool in 90nm process technology at a power supply voltage of 1.5V. Simulation results of both the logic circuits are compared and it is observed that transmission gate buffered full-adder circuit offers the lowest power delay product (a reduction of more than 45% value), which is the main objective in the implementation of high speed multimedia processors.