Ideal Behavior of Vernier and Flash TDCs Implemented in a Spartan-6 FPGA

In this paper, we will illustrate the working principle of the most popular time-to-digital converter (TDC) architectures in both application specific integrated circuits (ASIC) and field programmable gate array (FPGA) applications–- Vernier and tapped delay line (TDL) designs are used as a time interpolation method to yield a sub-clock period resolution. In order to understand their mechanism, Vernier and TDL-derived configurations are described first. Then, we propose a simulation work relying on fixing the finite propagation speed of each delay element of the delay chain to a delay equal to one or two clock cycles of the system clock period. That aims to assure the uniformity of the TDC binning and to eliminate the effect of process, voltage, and temperature (PVT) variations, which results in an ideal behavior of TDC that will be reflected in an ideal thermometer code. We have designed, implemented, and tested ideal TDCs in low-cost Spartan-6 FPGA, as well as by using the Xilinx ISIM tool.