SPHIRD–Single Photon Counting Pixel Readout ASIC With Pulse Pile-Up Compensation Methods

This brief presents the design and measurement results of a prototype SPHIRD-1 ASIC in the CMOS 40 nm process. The chip is dedicated to high count rate single photon counting operation at the European Synchrotron Radiation Facility with Extremely Brilliant Source. The core of the prototype IC is the matrix of
$64\times32$
pixels of
$50 \mu \text{m}$
pitch. Each pixel contains a Charge Sensitive Amplifier (CSA) with a fast discharge block and a detector leakage current compensation circuit. The CSA is connected to a set of three discriminators. The readout channel is equipped with additional circuits, which provide different pulse pile-up compensation methods. The priority of the analog front-end electronics is to process the input signal in a short time (the CSA output pulse time width is only 18 ns) and to keep low noise (the equivalent noise charge at the level of 188 el. rms) with a power consumption equals to
$26 \mu \text{W}$
/pixel. The chip is optimized for operation with a monochromatic X-ray beam with an energy of up to 30 keV. The measurements prove the possibility of counting up to 11.5 Gcps/mm 2 based on a 10% dead time loss input rate parameter.