Fault Tolerance and Cost Effectiveness Analysis of Low-Powered 3D-TESH Network

Exa-scale supercomputing is the prime target for the supercomputers. To reach at that point, supercomputers require redesigning the interconnection networks to support high network scalability, suitable network performance, low cost-performance ratio, low power usage, high fault-tolerance, low network congestion and high throughput with low latency. Among the thousand of interconnection networks, one of the most capable one is 3D-TESH, is a hierarchical interconnection network (HIN) interconnected with multiple basic modules (basic modules are basically treated as single on-chip network), where each on-chip network is similar to a 3Dmesh network and off-chip network are built using the 2Dtorus connections. Some static network parameters as well as dynamic communication performance (on-chip level) had been studied earlier for 3DTESH, which ensured the high significance of this network in comparing with others. Moreover, in case of power consumption, it requires about 41% less router power than 5Dtorus at the on-chip level. In this paper, we like to evaluate some other important static parameters like- packing density, fault tolerance, wiring complexity, cost effectiveness factor and etc. Here, we found that 3D-TESH yields much better results than network like - 3Dmesh, 2Dmesh, 2Dtorus, TESH and even the 3Dtorus.