An arbitration logic for CIF 30f/s bi-directional codec with graphic accelerator

In various multi-media system LSI based on H.32/spl times/, it is desirable to share one memory for cost effectiveness. We have designed an arbitration logic for a memory bus which is accessed by initiators frequently and simultaneously. We considered transaction of each initiator to determine a priority assignment for the bus access permission. This arbitration logic can exchange the priority assignment according to picture formats. This feature is realized by the mechanism which are named flexible priority control and round-robin control. We verified that the arbitration logic contributed to the improvement of the video codec processing performance.