Optimization of Ge Mole Fraction in Sacrificial Layers for Sub-3-nm Node Silicon Nanosheet FETs

Combinations of Ge mole fractions for performance optimization in NSFETs with S/D recess depth (T
SD
) variation were investigated using TCAD simulation. The inner spacer length (L
IS
) was set differently for each layer by controlling the Ge mole fraction of the SiGe sacrificial layer for performance optimization. In NSFETs with T
SD
variation, the performance was not optimized when all the L
IS
were set to 5 nm. The RC delay improved by 8.1% when the bottom L
IS
was shortened from 5 nm to 3 nm.