Offset-Canceling Current-Latched Sense Amplifier With Slow Rise Time Control and Reference Voltage Biasing Techniques

The current-latched sense amplifier (CLSA) is a promising candidate for detecting stored values in a memory cell. With technology shrinks, however, the input referred offset voltage (
$V_{\mathrm {OS}}$
) in the SA increases, resulting in a degradation of the memory read yield. To obtain a high read yield,
$V_{\mathrm {OS}}$
reduction and cancellation techniques have become essential in deep-submicrometer technology nodes. When determining the
$V_{\mathrm {OS}}$
in the CLSA, the voltage mismatch of the input NMOS pair is the dominant factor (
$\sim $
75%), followed by that of the latch NMOS pair (
$\sim $
25%). In this paper, 1) slow rise time (
$T_{\mathrm {RISE}}$
) control technique of SA enable signal and 2) reference voltage (
$V_{\mathrm {REF}}$
) biasing technique are proposed, and the effectiveness of the proposed techniques are analyzed for the conventional CLSA with footswitch (FS-CLSA) and offset-canceling CLSA (OC-CLSA). Post-layout based HSPICE simulation results using 28 nm model parameters show that the FS-CLSA with size-up strategy (OC-CLSA) achieves a 17.7% (10.5%) reduction of the standard deviation of
$V_{\mathrm {OS}}$
(
$\sigma _{\mathrm {OS}}$
) when a slow
$T_{\mathrm {RISE}}$
of 0.6 ns is employed. The measurement results from a 28 nm test chip show that the OC-CLSA with
$V_{\mathrm {REF}}$
biasing achieves a 22% reduction of
$\sigma _{\mathrm {OS}}$
compared to the conventional OC-CLSA.