Analysis of VCO jitter in chip-package co-design

Performance of a phase locked loop (PLL) is very dependent on the jitter in the voltage controlled oscillator (VCO). Traditionally, the jitter is analyzed on the basis of the nonidealities at the chip-level. In this paper, we demonstrate that package design could significantly impact jitter. Further, a novel methodology for analyzing the jitter of a VCO in a chip-package codesign methodology is presented, with the aid of an example. This methodology could easily be extended to include other sources of jitter, since there is no correlation between power supply noise and other sources. Good agreement between the theoretical prediction and simulation results is demonstrated.