High-Speed Data Transfer using AXI Protocol for Image Detection

Convolutional neural networks (CNN) due to their excellent accuracy, have emerged as the leading machine learning method. However, it becomes difficult to deploy CNN algorithms on hardware platforms because of their high memory bandwidth, computational complexity, and power consumption. Hardware accelerators such as Field Programmable Gate Arrays (FPGA), Graphics Processing Unit (GPU), etc. are excellent platforms for modelling CNN algorithms. The purpose of the paper is to run a standard software process in hardware and exploit natural parallelism in hardware to speed up neural network prediction. The paper presents a rule-based synthesizable Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) protocol for high-speed data transmission. The paper develops a computer vision system on an FPGA that could recognize the numbers 0 through 9 written by hand for the capstone design project. The findings show that 91% accuracy is achieved through Rectified linear activation unit (ReLU) which can be increased to 98% by implementing the Sigmoid activation function with a depth of 10 bits. The method provides good accuracy and clock performance while using few resources.