A 0.6-V 12-bit Set-and-Down SAR ADC With a DAC-Based Bypass Window Switching Method

This brief proposes a digital-to-analog-converter-based (DAC-based) bypass window switching method for the successive-approximation register analog-to-digital converter (SAR ADC). The proposed method defines the size of the bypass window by switching the designated capacitor in the DAC capacitor array to achieve low power for a small input amplitude. If the input falls within the window, some switching phases can be skipped to save power consumption. Since this switching method only utilizes the existing DAC capacitor array and a few additional digital circuits for window definition, it can be employed in SAR ADC architectures with a variable input common-mode voltage during conversion operation, such as set-and-down SAR ADCs. The operation of the proposed bypass window switching is verified with a 12-bit set-and-down SAR ADC fabricated in TSMC
$0.18~\mu \text{m}$
CMOS process. At the sampling rate of 50 kHz, the total power consumption is
$1.54~\mu \text{W}$
from a 0.6-V supply with a 760-mVpp 24.95-kHz input. The power consumption with a 20-mVpp input that all falls in the window can be significantly reduced to
$0.49~\mu \text{W}$
. The measured signal-to-noise and distortion ratio and spurious-free dynamic range with 760-mVpp 24.95-kHz input and 50-kS/s sampling rate are 62.67 and 82.44 dB, respectively, resulting in the effective number of bits of 10.12. Based on the power consumption of
$1.54~\mu \text{W}$
, the Walden figure of merit is 27.7 fJ/conversion-step.